FEATURES:
- Support different modes of configuration
- Asynchronous WRITE and READ FIFO
- Synchronous WRITE and READ FIFO
- Synchronous WRITE and READ FIFO, without WE input
- Asynchronous WRITE and READ FIFO, without full and empty outputs
- Support input data Randomization
- Multiple clocks support
- Multiple Ready Test Scenarios
- Reset configuration support
- Driver,Monitor, Scoreboard classes functions customization support
- Assertions Support
- Coverage Support
- Events and Callbacks Support
- Customized Messaging
- Ready test scenarios
- FIFO full and empty states checking
- Post-Synthesis Timing Simulation support
- Xilinx FPGA Support
- Transaction Recording
- Automation Scripts
- VIP Documentation
BENEFITS:
- All System verilog written classes can be reused
- Runs in every major simulators environment.
- Runs in Xilinx FPGA
- On-Live SystemVerilog and UVM 2 day Training
- Support for VIP understanding, configuration and integration
- DUT Documentation Creation
- Automation Scripts development
- DUT DRC Rule Check using in-house tools
- Support for Verification Flow Development
For any inquiries Please Contact US.