Release Date: January 15 th , 2017
Verification IP for the DDR controller arbiter module. When there are multiple data domains which should write data to the DDR memory through the DDR controller, there exists DDR arbiter module which makes arbitration between different data domains. The main role of DDR arbiter module is make sure that each data domain access to the DDR controller based on its priority, no data domain priority is violated. The DDR controller arbiter verification ip provides environment to test DDR controller arbiter designs.
FEATURES:
- Supports any type of DDR controller
- Supports multiple modes such as Write, Read, Hold and so on
- User Controllable Write Channels Number
- User Controllable Read Channels Number
- Parametric Clock Frequency
- Different versions of DDR memories such as DDR3,DDR2
- Multiple ready test scenarios
- Low Power Modes Support
- Glitch monitor and injection.
- Callbacks and events for user customization
- User Ports
- Status counters for various events in bus.
- Assertions support
- Functional coverage
- Driver class functions customizations
- Monitor class functions customization
- Scoreboard class functions customization
- Support for customer comparisons
- Automation Scripts
- Documentation
BENEFITS:
- Runs in every major simulators environment.
- Runs in Xilinx FPGA
- Free On-Live SystemVerilog and UVM 2 day Training
- Support for VIP understanding, configuration and integration
- DUT Documentation Creation
- Automation Scripts development
- DUT DRC Rule Check using in-house tools
- Support for Verification Flow Development