Here you can find Free Verification IPs written in System Verilog code. At this stage only 2 VIPs are available: • FIFO • SPI However we are continuously developing new […]
FIFO
FIFO System Verilog Based VIP This is a verification mechanism for the asynchronous FIFO. As an asynchronous FIFO design Cliff Cummings FIFO design was used, which is described in following article […]
SV SPI
Serial Peripheral Interface (SPI) SV based VIP This is a verification mechanism for the SPI devices. As an DUT the design from Open Cores was used. FEATURES: Master mode support Support […]