FEATURES: Support different modes of configuration Asynchronous WRITE and READ FIFO Synchronous WRITE and READ FIFO Synchronous WRITE and READ FIFO, without WE input Asynchronous WRITE and READ FIFO, without […]
UVM Verification IP
Here you can find Free Verification IPs written in UVM and System Verilog code. At this stage only 3 VIPs are available: • FIFO • SPI • LCD Driver However […]
UVM FIFO
FIFO UVM Based VIP This is a Verification IP for the asynchronous FIFO. As an asynchronous FIFO design Cliff Cummings FIFO design was used, which is described in following article […]
UVM SPI
Serial Peripheral Interface (SPI) UVM based VIP This is a verification mechanism for the SPI block. As a DUT the SPI module from Open Cores was used. FEATURES: Supports exact SPI […]