These are free Verification IPs written in System Verilog language.
FIFO System Verilog Based VIP This VIP is for the asynchronous FIFO as a DUT. It is based on Cliff Cummings FIFO design. FEATURES: Supports constraints Randomization Support input write […]
SPI: The SPI Verification IP is fully compliant with Version 2.00 MIPI STP specification and verifies the System Trace Protocol Interface. It includes an extensive test suite covering most of […]