UVM SPI

Serial Peripheral Interface (SPI) UVM based VIP

This is a verification mechanism for the SPI block.  As a DUT the SPI module from Open Cores was used.

FEATURES:

• Supports exact SPI device
• Master mode support
• Slave mode support
• Support for multiple slaves
• Multiple Transmission Mode support [Reduced]
• Support for Send Data Randomization
• Support internal clock division check [Reduced]
• Built in functional coverage analysis [Reduced]
• Mechanism to specify Master generates SCLK frequency – e.g. divide one of its input clocks to the given value [Reduced]
• Support for Baud Rate Control [Reduced]
• Support for Low Power Mode testing [Reduced]
• Mechanism to control the periods of test-bench generated clocks [Reduced]
• Self-checking testbench
• Integrated Register Package [Reduced]
• Assertions Support [Reduced]
• Coverage Support [Reduced]
• Events and Callbacks Support [Reduced]
• Customized Messaging [Reduced]
• Ready test scenarios [Reduced]
• Automation Scripts [Reduced]
• Documentation [Reduced]

BENEFITS:

• Runs in every major simulators environment.
• Support for VIP understanding, configuration and integration (only if code is used in educational or scientific purposes)

Please feel free to add any comments that you have related to this VIP.