FEATURES:
- Supports SPI Specification written in
- Motorola S12SP1V3/D SPI Block Guide V03.06
- SPI bus specification as defined in M68HC11 user manual rev 5.0
- OIF-SPI-4-02.1
- Slave device support for BOSCH SMB380 and RICOH R2033K
- Master mode support
- Slave mode support
- Support for multiple slaves
- Multiple Transmission Mode support
- Support clock polarity (CPOL) selection
- Support clock phase (CPHA) selection
- Support MSB/LSB first data transmission
- 8/16/32/64 bit wide Transmit/Receive Data Path, support data width from 4 to 64 bits
- Support internal clock division check
- Support single and burst transfer mode
- Glitch insertion and detection
- SPI Slave can be configured as standard device or can use FIFO for data passing.
- Mechanism to specify Master generates SCLK frequency – e.g. divide one of its input clocks to the given value
- Support for Baud Rate Control
- Bidirectional Mode support (MOMI or SISO)
- Support for Low Power Mode testing
- Wait and Stop Modes support
- Error Conditions testing support
- Mechanism to control the periods of test-bench generated clocks
- Integrated Register Package
- Assertions Support
- Coverage Support
- Events and Callbacks Support
- Customized Messaging
- Ready test scenarios
- Driver, Monitor, Scoreboard class functions customization
- Automation Scripts
- Documentation
BENEFITS:
- All System Verilog classes can be reused
- Runs in every major simulators environment.
- Runs in Xilinx FPGA
- Free On-Live SystemVerilog and UVM 2 day Training
- Support for VIP understanding, configuration and integration
- Automation Scripts development
- DUT DRC Rule Check using in-house tools
- Support for Verification Flow Development
For any inquiries Please Contact US.