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YanSolutions > Archive for System Verilog VIP

Category: System Verilog VIP

System Verilog VIP

Sunday May 29th, 2016Friday September 30th, 2016 user

Here you can find Free Verification IPs written in System Verilog code. At this stage only 2 VIPs are available: • FIFO • SPI However we are continuously developing new […]

System Verilog VIPalpha tester, education, FIFO, Free VIP, Scientific, SPI, trainingLeave a comment

FIFO

Wednesday June 1st, 2016Friday September 30th, 2016 user

FIFO System Verilog Based VIP This is a verification mechanism for the asynchronous FIFO.  As an asynchronous FIFO design Cliff Cummings FIFO design was used, which is described in following article […]

FIFOLeave a comment

SV SPI

Wednesday June 1st, 2016Friday September 30th, 2016 user

Serial Peripheral Interface (SPI) SV based VIP This is a verification mechanism for the SPI devices.  As an DUT the design from Open Cores was used. FEATURES: Master mode support Support […]

SPI1 Comment
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