SPI

SPI:

The SPI Verification IP is fully compliant with Version 2.00 MIPI STP specification and verifies the System Trace Protocol Interface. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create most wide range of scenarios to verify the DUT effectively.

FEATURES:

• Supports version 2.00 MIPI STP Specification.
• Supports a trace stream comprised of 4-bit frames.
• Supports for merging trace data from up to 65536 independent data sources (Masters).
• Supports up to 65536 independent data Channels per Master.
• Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data.
• Supports Time-stamped data packets using one of several time stamp formats including:
• Gray code
• Natural binary
• Natural binary delta
• Export buffer depth (legacy STPv1 timestamp that requires DTC support).
• Supports Data packet markers to indicate packet usage by higher-level protocols.
• Supports Flag packets for marking points of interest (for higher-level protocols) in the stream.
• Supports Packets for aligning time stamps from different clock domains.
• Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC.
• Supports Packets for cross-synchronization events across multiple STP sources.
• Supports for user-defined data packets.
• Facilities for synchronizing the trace stream on bit and message boundaries.
• Supports all types of error insertion and detection.
• Invalid Time-stamp format
• Invalid opcode
• Invalid async pattern
• Invalid version
• Glitch insertion and detection.
• Supports constraints Randomization.
• Status counters for various events in bus.
• Callbacks in Master and Slave for various events.
• MIPI STP Verification IP comes with complete testsuite to verify each and every feature of MIPI STP specification.
• Functional coverage for complete MIPI STP features.

BENEFITS:

• Compatible with testbench writting using VIP’s
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment.
• Runs in custom FPGA platforms