FIFO System Verilog Based VIP
This is a verification mechanism for the asynchronous FIFO. As an asynchronous FIFO design Cliff Cummings FIFO design was used, which is described in following article “Simulation and Synthesis Techniques for Asynchronous FIFO Design”.
FEATURES:
- Support input data Randomization
- Multiple clocks support
- Mechanism to control the periods of test-bench generated clocks
- Self-checking testbench
- Assertions Support
- Ready test scenarios
- FIFO full and empty states checking
- Documentation
BENEFITS:
- All System verilog written classes can be reused.
- Runs in every major simulators environment.
- Free Support for VIP configuration and integration (only if code is used in educational or scientific purposes).
Please feel free to add any comments that you have related to this VIP.