Serial Peripheral Interface (SPI) SV based VIP

This is a verification mechanism for the SPI devices.  As an DUT the design from Open Cores was used.


  • Master mode support
  • Support for multiple slaves [reduced]
  • Support for Send Data Randomization
  • Support internal clock division check [reduced]
  • Mechanism to specify Master generates SCLK frequency – e.g. divide one of its input clocks to the given value
  • Support for Baud Rate Control [reduced]
  • Support for Low Power Mode testing [reduced]
  • Mechanism to control the periods of test-bench generated clocks [reduced].
  • Self-checking testbench
  • Assertions Support [reduced]
  • Coverage Support [reduced]
  • Ready test scenarios [reduced]
  • Automation Scripts [reduced]
  • Documentation [reduced]


  • Runs in every major simulators environment. [reduced]
  • Support for VIP understanding, configuration and integration, [only if the codes are going to be used for educational or scientific purposes]
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