This is a Verification IP for the asynchronous FIFO.
As an asynchronous FIFO design Cliff Cummings FIFO design was used, which is described in following article “Simulation and Synthesis Techniques for Asynchronous FIFO Design”.


  • Support different modes of configuration (reduced)
  • Asynchronous WRITE and READ FIFO
  • Synchronous WRITE and READ FIFO
  • Synchronous WRITE and READ FIFO, without WE input
  • Asynchronous WRITE and READ FIFO, without full and empty outputs
  • Support input data Randomization
  • Multiple clocks support
  • Multiple Ready Test Scenarios (reduced)
  • Reset configuration support (reduced)
  • Self-checking testbench
  • Assertions Support (reduced)
  • Coverage Support (reduced)
  • Ready test scenarios ( reduced)
  • FIFO full and empty states checking
  • Automation Scripts (reduced)
  • VIP Documentation (reduced)


  • Runs in every major simulators environment.
  • Support for VIP understanding, configuration and integration (only if code is used in educational or scientific purposes)

Get View code
Please feel free to add any comments that you have related to this VIP.

Leave a Reply

Your email address will not be published. Required fields are marked *