Release Date: December 15 th , 2017
I2C Verification IP provides an smart way to verify the I2C bi-directional two-wire bus. The I2C Verification IP is fully compliant with version 2.1 and 3.0 of the Philip's I2C-Bus Specification and provides the following features.
I2C VIP is supported natively in Verilog and VHDL
FEATURES:
- Supports 6.0 I2C Specifications.
- Supports standard, fast, fast mode plus and high speed operations.
- Full I2C Master and Slave functionality.
- Operates as a Master, Slave, or both.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Supports all I2C clocking speeds.
- 7b/10b configurable slave address.
- Support bus arbitration for multi master.
- Supports multiple slaves.
- Supports insertion of wait states by slave and master.
- Supports injection of various of errors.
- Master aborting in middle of access.
- Master doing ACK on last read access.
- Master continue after NAC from slave for write data.
- Glitch injection on clock and data at various windows.
- Compares read data with expected results.
- Bus-accurate timing.
- Various kind of Master and Slave errors generation.
- Glitch monitor and injection.
- Callbacks in master and slave for various events.
- Status counters for various events in bus.
- Functional coverage to cover all functionality of I2C slave and master.
BENEFITS:
- Faster testbench development and more complete verification of I2C designs.
- Runs in Xilinx FPGA
- On-Live SystemVerilog and UVM 2 day Training
- Support for VIP understanding, configuration and integration
- DUT Documentation Creation
- Automation Scripts development