FIFO System Verilog Based VIP

This VIP is for the asynchronous FIFO as a DUT.  It is based on Cliff Cummings FIFO design.


  • Supports constraints Randomization
  • Support input write data and read data comparision
  • TB checks the write and read data ordering, make sure that they much
  • FIFO full and empty states checking
  • Support multiple clocks
  • Support assertions


  • All System verilog written classes can be reused
  • Runs in every major emulators environment.
  • Runs in custom FPGA platforms
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