FIFO UVM Based VIP
This VIP is for the asynchronous FIFO as a DUT. The FIFO has developed for Cliff Cummings FIFO, written in his article. However the VIP supports all possible configurations of the FIFO.
- Asynchronous WRITE and READ FIFO
- Synchronous WRITE and READ FIFO
- Synchronous WRITE and READ FIFO, without WE input
- Asynchronous WRITE and READ FIFO, without full and empty outputs
- Supports constraints Randomization.
- Supports a trace stream comprised of 4-bit or any-bit frames.
- Supports all types of error insertion and detection
- Functional coverage for complete features.
- Support multiple clocks
- Support SDF annotated timing simulation
- Support for Assertions check
- Support all possible power down and up models
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment.
- Runs in custom FPGA platform